Probe Wiring Guide

7.1

Power in: pack, gauge, charger, and J5

What this is

The pack's two wires reach the charger through the fuel gauge, and the charger's LIPO and GND pads hand the same node to J5. The charger is the Adafruit #4755 (bq24074) since 15 October (ADR 0018); the bq25185 it replaced has no thermistor pad, see the note below. The pack itself — cells, bus bars, fuse, plug — is the Battery Pack page; this chapter starts at its plug.

Parts

• The built pack with its 1.6 A fuse and JST-PH plug (Battery Pack page)
• MAX17048 #5580 — 1
• bq24074 charger #4755 — 1
• JST-PH lead with a plug at each end — 1
• 20 AWG silicone wire, one orange (or red) and one black, long enough to reach the daughter board
• 10 kΩ NTC thermistor (Vishay NTCLE100E3103JB0) — 1, and a 200 kΩ resistor — 1, on about 150 mm of thin twisted pair, with a 2-pin XH break (B2B-XH-A and XHP-2) near the charger and red heat-shrink for the pair's twisted joints
• A hobby knife, and tape for the Load Out socket
• The solar pair from the combiner, its far ends bare (§7.2)

Drawing

Steps

1. The gauge goes inline — this is settled. Once its plug has passed the sign check above, the pack's plug goes into the gauge's left JST-PH port, board silkscreen up; a lead from the right port goes to the charger's LiPo Batt socket — never Load Out, which is a regulated output and would charge a pack plugged into it toward 4.4 V [D]. The two gauge ports are electrically the same (Adafruit: “connect the battery to either one, then the load/charger to the other”); left and right is a convention so every board can be checked against one picture.
2. Modify the charger before it is ever powered — three things, in this order, each checked (ADR 0018). First the THERM link (the spec and the drawing call it THM), the printed bar between two dots just above the THERM pad: cut it with the knife, then meter THERM to GND — open, megohms or OL. A partial cut leaves the board's own 10 kΩ in parallel with the thermistor and the cold gate can then never trip; the open check must come first, and afterwards a reading below about 6.5 kΩ at room temperature [C] says the link is still there. Second, the charge-rate links: cut 1.0A, bridge the 0.5A pads with a blob of solder; meter ISET to GND: 2.0 kΩ [C] — 1.99 kΩ was read [M] on charger 1 (1.0 kΩ means unmodified; 667 Ω means the 1.0A link survived and the charge would be 1.33 A; the cut link's own pads read 3 kΩ, never open — all [C]). Then the back-side EN1/EN2 jumpers: EN2 to OUT and EN1 to GND each a beep — they arrived bridged [M] though the board file shows both open, and both open means a 100 mA input limit. Third, tape over Load Out.
3. Solder the thermistor pair to THERM and the GND beside it, through a 2-pin XH break near the charger so the pack and the charger can part without unsoldering; label it, it is not keyed — the solar lead's XHP-2 fits it too. The 10 kΩ NTC and the 200 kΩ resistor in parallel at the far end of the twisted pair, so the bead can sit against a cell later; cover the pair's twisted joints with heat-shrink — bare, they leaked in the ice bag and the bead read +8 °C warm [M]. The gate was measured by ice on all three chargers and accepted as built on 2026-11-03 (ADR 0018, decision 3): charger 1 stops at about −2.3 °C, charger 2 at about −2.0 °C, charger 3 between −0.4 and −1.0 °C, and all three resume just above 0 °C [C]. The bare thermistor would stop at about +3 °C [C], inside the water SEA floats in. An unplugged pair reads as cold and the charger stops: keep the break plugged in whenever the charger has power.
4. Solder the orange 20 AWG wire to LIPO and the black one to the GND pad next to it, at the right end of the row. Heatshrink is not possible on a pad, so add strain relief at the wire (a dab of hot glue or a tie to the board's mounting hole), never on the joint itself.
5. Solder the solar pair into the two Opt. Cap holes: the marked lead into VBUS, the other into GND. It is soldered, not plugged, and it goes in the holes rather than the edge row because a through-hole holds a wire. Mind the polarity more than anywhere else on this page: VBUS sits after the board's own input diodes, so a swapped pair puts the panels' negative on a pin rated −0.3 V [D] and kills the chip.
6. Land them on J5: orange to pin 1, black to pin 2. Leave the charger's USB-C socket and its DC jack empty in flight; the USB-C is the bench's way of charging a pack.

7.2

Solar: three panels, three diodes, one pair

What this is

Each panel feeds the charger through its own Schottky diode, so a shaded panel cannot pull current out of the lit ones. The diodes live on a small combiner board next to the panels, so only one solar pair crosses the equator to the charger. The flight probes use a fabbed board, meteo-solar-combiner (ordered 2026-10-03, arrived 2026-10-15, five boards): three SS14 diodes placed by the fab, a pad pair and a strain-relief hole for each panel's leads, one 2-pin JST-XH header, and five meter pads — TP1–TP3 on each panel before its diode, TP4 on the output, TP5 on ground. A scrap of perfboard with three 1N5817 is the same circuit built by hand. Either way the panels' leads are soldered to the combiner, with no connector: the panels are bonded into the shell the combiner sits in, and the two never part. As built, every panel lead ends in an XH plug into a socket on the combiner's pad pair, on all three combiner boards; accept the plugs or solder is open (FW-29). The second set's plugs were crimped red to minus and caught by the sign check.

Parts

• Voltaic P123 — 3 (solder pads marked V+ and V− on the back)
• The solar combiner board, its three SS14 placed — 1; or a scrap of perfboard (the ElectroCookie mini will do) and 1N5817 — 3
• JST-XH 2-position header (B2B-XH-A) — 1; housing (XHP-2) — 1
• Pre-crimped 22 AWG JST-XH lead, 305 mm — 2; both are black, so red heatshrink to mark one; no document records the platform-to-deck distance this pair must span
• 24 AWG silicone wire, red and black, for the panels' leads
• 1 kΩ resistor, for the check — 1

Drawing

Steps

1. Leads on the panels. Red to V+, black to V−, 24 AWG silicone. The panel is live in any light and the far ends of its leads are bare: keep it covered — face down, or taped over — from now until both leads are soldered to the combiner.
2. Prove each panel's polarity before it is bonded into the hull. Uncover it, red probe on the red lead, black on the black: a positive reading. Cover it again. After bonding, a reversed panel is a destructive rework.
3. Diodes on the combiner, band toward the output. On the fabbed board they arrive placed. On a perfboard each panel's red will go to a diode's plain end (anode); the three banded ends (cathodes) join into one positive bus, and the three blacks into one negative bus. Run the diode check below before any panel is soldered in.
4. Solder each panel's leads to the combiner — no connector. Both wires go through the strain-relief hole first, so a pull lands on the board and never on a joint; red to the rectangular + pad. On a perfboard, lace them through a spare hole the same way. (Built plugged, as above: sign-check each panel plug first.)
5. One JST-XH header on the output, pin 1 = +, and one pair down. Mark one of the two black leads red at both ends; the marked one goes in cavity 1 of the housing, the + side. At the charger the pair is soldered into the Opt. Cap holes, VBUS and GND, not plugged — §7.1.

7.3

The board's power section: J5 → F1 → U1 → JP1

What this is

The fuse, the regulator and its three capacitors make the always-on 3.3 V rail. JP1 is the rail's on/off switch, and later the place a meter goes to measure what the probe draws.

Parts

• 2.54 mm screw terminal, 2-way (J5) — 1
• Polyfuse, 1.1 A hold (F1) — 1
• MCP1700-3302E/TO (U1) — 1
• 1 µF ceramic (C1, C2) — 2; 10 µF ceramic (C3) — 1
• 2-pin header + shunt (JP1) — 1
• Short links: red and black 22 AWG

Drawing

Steps

1. Under the board first: the two rail ties (+ rails at column 3, − rails at column 6), and leave room for the orange VBAT wire from column 1 (§7.10) and the black modem return into column 3, hole i.
2. Links: column 2 to column 3 (hole g, black — J5's ground has no rail hole of its own, because J5's body covers it); column 3 to the − rail at column 3; column 6 to the + rail at column 6.
3. C1 across columns 3 and 4 (hole f); C2 from column 5 to the − rail at column 5, C3 from column 5 to the − rail at column 4. Ceramic capacitors have no polarity.
4. U1. Find pin 1 on the real part first: hold it flat, marked face toward you, legs down — Microchip's drawing then reads 1 GND, 2 VIN, 3 VOUT left to right (DS20001826E, Package Types; Table 3-1). Put its legs in columns 3, 4, 5 (hole h) with the flat face toward the bottom edge, so pin 1 lands in column 3.
5. F1 from column 1 (hole h) to column 4 (hole g), bending the legs to fit.
6. JP1 in columns 5 and 6 (hole g). Leave the shunt off.
7. J5 last, pin 1 in column 1, pin 2 in column 2, hole j, wire entries facing the bottom edge.

7.4

The fifteen wires to the DFR0923

What this is

3V3, ground and thirteen signals, one 22 AWG solid wire each, from the daughter board to the shield's screw terminals. The FireBeetle plugs into the shield last, after every wire is checked.

Parts

• FireBeetle 2 ESP32-E (DFR0654-F, headers fitted) — 1
• The DFR0923 shield — 1
• 22 AWG solid hookup wire in the eight colours below
• Paper flags or a label maker for the IO numbers

Drawing

Steps

1. Shield first, empty. Leave its 7–24 V input terminal and the 5V terminals empty — nothing on this probe uses them — and set the LED switch to off: the wiki puts a status LED on every terminal but GND.
2. Cut each wire to length with some slack, strip both ends, and flag both ends with the IO number before soldering anything.
3. Board end: solder each wire into a free hole of the column the table gives. Solid wire, because it stays where you put it on a board.
4. Shield end: strip a little at a time until the bare copper reaches the back of the clamp with none showing outside it. Insert, tighten, tug. One wire per terminal.
5. Plug the FireBeetle in last, the right way round — match its pin labels to the shield's.

7.5

The sensor bus, I²C0: QW1, the BMP581, the BME280 seat

What this is

The always-on bus on IO21/IO22: the fuel gauge on QW1, the barometer in SOCK_BARO, and the BME280 in a seat of its own.

Parts

• 4-way female header (QW1 bench socket) — 1, and one owned Qwiic-to-male-header cable
• 7-way female header (SOCK_BARO) — 1
• 4-way female header (the BME280 seat) — 1
• The BMP581 with a 7-pin header soldered on once; the BME280 SEN-13905
• Blue and yellow 22 AWG for the links

Drawing

Steps

1. QW1 in columns 1–4: pin 1 GND, 2 3V3, 3 SDA0, 4 SCL0. The owned Qwiic cable plugs the gauge's Qwiic socket into it; the proto card records its leads as red 3V3, blue SDA, yellow SCL (and black GND) — ring them before trusting that.
2. The BMP581's header, once: cut the supplied header to 7 pins and solder it to the board's seven holes. Leave both of its solder jumpers as shipped: I2C ADDR at its default, 0x47, and I2C_Pull_Up untouched — its pull-ups are part of the bus's total.
3. SOCK_BARO, 7-way, in columns 5–11, so all seven pins are held and an offset is impossible. Pins 1–3 (INT, SDO, CSB) connect to nothing; 4 SDA, 5 SCL, 6 GND, 7 3V3.
4. The BME280 seat — SOCK_BME in the CSV since 2026-10-02, drawn dashed. A 4-way female strip in columns 12–15 for the board's I²C row, which the datasheet note lists as GND, 3.3V, SDA, SCL. It is unkeyed: mark pin 1 (GND) on the board in ink. If your BME280 also has its 6-pin SPI row soldered, it will overhang the seat on one row — note how it sits, and support it (§9). The fabbed carrier answers this with a second, 6-way socket that is mechanical only.
5. The links: blue column 3→8→14 (SDA0), yellow column 4→9→15 (SCL0), and each GND and 3V3 column to its rail.

7.6

The GPS bus, I²C1: U2, R1, QW2

What this is

A load switch, U2, gives the GPS 3.3 V only while IO25 is high, and the GPS has a bus of its own on IO18/IO19. Left on the sensor bus with its rail off, it would leak about 2 mA [C] backwards through its protection diodes from the other boards' pull-ups (carrier spec, “The backfeed problem”). That is why nothing from the sensor bus goes on this bus. One board does ride on it: since 2026-11-03 a second BMP581 plugs into the GPS's second Qwiic port, sits on I²C1 at 0x47 and has power only while the GPS rail is up (whether it stays there is FW-29's).

Parts

• TPS22918 on a SOT-23-6 adapter (U2) — 1
• 100 kΩ (R1) — 1
• 4-way female header (QW2 bench socket) — 1, and one owned Qwiic cable
• The SAM-M8Q, GPS-15210, and the SparkFun Qwiic BMP581 (SEN-20171) on its second port, with one Qwiic cable

Drawing

Steps

1. Solder U2 onto its adapter (the fiddly joint — §5). The pin map, from the TI datasheet note: 1 VIN, 2 GND, 3 ON, 4 CT, 5 QOD, 6 VOUT, top view.
2. Ring the adapter: each chip pin to its adapter pin, and no pin to its neighbour. Write the pin numbers on the adapter.
3. Seat it across the channel in columns 22–24, pins 1–3 in the bottom half, so: 22B VIN, 23B GND, 24B ON; 22T VOUT, 23T QOD, 24T CT.
4. QOD connects to nothing; CT takes a 4.7 nF capacitor to ground. QOD floating disables the output discharge. CT was left floating too when this page was drawn, and the drawings still show it so — but the reviews of the fabbed carrier on 2026-10-02 found that a floating CT switches the rail on in about 0.1 ms [C], fast enough for a breakout's capacitors to drag the 3.3 V rail toward the ESP32's brown-out. The ordered board carries 4.7 nF on each switch's CT pin (C8, C9) for a rise of a few milliseconds. On this board: one 4.7 nF ceramic from each switch's CT strip (24T for U2, 21T for U3) to the nearest − rail.
5. R1 from column 24 to the − rail at column 24; the IO25 wire into column 24; links 22B → + rail, 23B → − rail; a red link 22T → 26T.
6. QW2 in top columns 25–28: 1 GND, 2 3V3_GPS, 3 SDA1, 4 SCL1; link 25T → − rail.
7. Never cut the SAM-M8Q's I2C jumper. Its two 2.2 kΩ resistors are the pull-ups on this bus, and they are what make the backfeed fix work; whether the second BMP581's board adds any of its own is not recorded.
8. The second BMP581 plugs into the SAM-M8Q's second Qwiic port and answers at 0x47 only while IO25 is high.

7.7

DS18B20 on J8

What this is

The sea or ground temperature probe on 1-Wire, IO4, with its 4.7 kΩ pull-up on the board. Its lead, the gland and why it has three wires are the Thermal Probe page.

Parts

• 2.54 mm screw terminal, 3-way (J8) — 1
• 4.7 kΩ (R3) — 1
• The DS18B20 probe

Drawing

Steps

1. R3 from column 15 to column 17 (hole h); the IO4 wire into 15. Column 16 (J8's ground) reaches the − rail through a wire under the board to the rail at column 18; column 17 (3V3) is linked to column 18, and column 18 to the + rail — J8's own rail holes are under its body.
2. J8 in columns 15–17: pin 1 OW_DATA, 2 GND, 3 3V3.
3. Identify the probe's three wires with the meter before they go near J8 (HULL-28): only board 1's probe has been rung out, by diode test on 2026-10-15 (black = GND [M]; red and yellow by the convention) — the other two have not, and reversing VDD and GND destroys a sensor there is no spare of. Use the DS18B20's own datasheet pinout and the meter's diode test between the wires.

7.8

The carrier's NTC on J7

What this is

A 10 kΩ thermistor at the pack, in a divider with R4, read by IO39. IO13 powers the divider only for the hourly read, so it draws nothing the rest of the time. This is the reporting thermistor; the charger's own one is the pair of §7.1 (ADR 0018).

Parts

• 2.54 mm screw terminal, 3-way (J7) — 1
• 10 kΩ (R4) — 1
• 10 kΩ NTC, B 3977 K [D], leaded — 1, with a two-wire lead to the pack (15 are owned: see Parts and tools)

Drawing

Steps

1. R4 from column 9 to column 10 (hole g) — column 10 is the gap after J7 and a ground strip, linked to the − rail at column 10. The IO13 wire into 7, the IO39 wire into 9.
2. J7 in columns 7–9: pin 1 SENSE_EXC, 2 vacant, 3 NTC_SENSE. The thermistor's two legs go to terminals 1 and 3; the centre terminal stays empty.
3. Why the centre stays empty: the harness rule builds NTC and leak leads as 3-position, centre-vacant, so the same lead later fits the fabricated board's JST-XH port and cannot offset-mate it with one contact dead.

7.9

Leak sense on J9

What this is

Two pads in the hull, normally an open circuit. IO13 excites them through R5 only during a read; water across the pads pulls IO35 down. C6 gives the ADC the low source impedance it wants: τ = R5·C6 = 100 kΩ × 100 nF = 10 ms [C], which is why firmware waits 50 ms before reading.

Parts

• 2.54 mm screw terminal, 3-way (J9) — 1
• 100 kΩ (R5) — 1; 100 nF ceramic (C6) — 1
• The lead to the hull pads (the pads themselves belong to the sealing cycle)

Drawing

Steps

1. R5 from column 7 to column 11 (hole f); C6 from column 11 to the ground strip in column 10 (hole h); link column 13 (J9's ground) to column 14, and column 14 to the − rail; the IO35 wire into 11.
2. J9 in columns 11–13: pin 1 LEAK_SENSE, 2 vacant, 3 GND. The pad lead uses terminals 1 and 3.

7.10

The RockBLOCK: U3, JP2, J6, and the antenna

What this is

The modem runs straight from the pack: VBAT, tapped before F1, through load switch U3 on IO26 and jumper JP2 to J6 pin 1 and the modem's pin 8 (ADR 0014). The modem takes 3.0–5.4 V [D] there and buffers its own transmit burst; the supply sees at most 470 mA [D], and the charge peak measured 0.45 A across JP2 [M].

Where the modem sits. Since 2026-10-20 the RockBLOCK hangs under the solar deck in the crown (a 3 mm plate at z +42 to +45, right under the antenna), not on the main platform; its bay is 45 × 45 mm with no clearance yet (HULL-34). No document records the platform-to-deck distance the J6 lead must span: do not cut the modem's cable, or the five wires from J6, to length until it is measured.

Parts

• TPS22918 on a SOT-23-6 adapter (U3) — 1
• 100 kΩ (R2) — 1; 2-pin header + shunt (JP2) — 1
• 2.54 mm screw terminal, 5-way (J6) — 1
• 20 AWG wire: orange for VBAT under the board and JP2 → J6:1; black for the modem's return
• The modem's 10-way cable
• The Amphenol 135110 cable and the Maxtena antenna

Drawing

Steps

1. U3 onto its adapter, ring it, seat it across the channel in columns 19–21 exactly as U2: 19B VIN, 20B GND, 21B ON; 19T VOUT, 20T QOD, 21T CT — QOD connects to nothing, and CT takes its 4.7 nF to the − rail as on U2 (§7.6).
2. The VBAT wire, under the board: 20 AWG orange from column 1 to column 19. It is the only wire that taps the pack before the fuse, deliberately: a polyfuse's resistance would eat the modem's margin against its 3.0 V minimum [D].
3. R2 from column 21 to the − rail at column 21; the IO26 wire into 21; link 20B → − rail; a short 20 AWG orange link 19T → 18T.
4. JP2 in top columns 18 (pin 1) and 17 (pin 2), hole c, shunt off; a 20 AWG orange wire under the board from 17T to 26B.
5. J6 in columns 26–30, in the CSV's order: 1 VBAT_RB_SW, 2 GND, 3 RB_RX, 4 RB_TX, 5 RB_ONOFF. J6's rail holes are under its body, so its ground (column 27) reaches ground by a 20 AWG black wire under the board to column 3, hole i, beside J5 — which also keeps the modem's return current off the thin rail.
6. The modem's cable. Ground Control's knowledgebase: the 9603's user connector is a Molex PicoBlade, 1.25 mm pitch, 10-way, mating part 51021-1000. No cable shipped with the two owned units. A pre-crimped MX1.25 kit (PicoBlade-compatible) fits — one is owned, the Cermant 2–10P kit (28 AWG, 150 mm) — and fills only the five positions J6 uses; its 150 mm is the kit's, not a measured need. Ground Control's own tails cable carries all ten. Pin 1 is not marked on the modem's board: it is the end of the header away from the mounting hole beside it. Whichever cable is used, ring each wire to its connector pin and flag it.
7. J6 to the modem, by Ground Control's pin table: J6:1 → pin 8 (“5v In” — the pin their power page says a 3.7 V Li-ion source connects to directly); J6:2 → pin 10 GND; J6:3 (the ESP32 transmits, IO17) → pin 6 TXD, which their table calls “Iridium TX (input)”; J6:4 (the ESP32 receives, IO16) → pin 1 RXD, “Iridium RX (output)”; J6:5 → pin 7 OnOff. Pin 9 is labelled “Li-Ion” and is not used: it sits behind the RockBLOCK's own internal diode (D1 in ADR 0014). Pins 2–5 stay unconnected.
8. Both power controls are wired. U3 cuts the whole rail; J6:5 drives the modem's own On/Off pin, which on the owned v3.D units is ordinary logic — off below 2.0 V, on above 2.4 V [D]. Which one the firmware uses is a measurement, FW-10 (ADR 0014, “The On/Off trade”), which FW-07's supercapacitor test settles first. Whether a v3.D modem treats an undriven On/Off pin as on is not recorded, so firmware must drive IO14 high during a window either way — though the audit of 2026-10-15 holds this fails on a Rev F modem with a full pack (FW-25). (The datasheet note's “leave On/Off floating” is the Rev F rule, which ADR 0014 superseded for these boards.)
9. The antenna link. The Amphenol cable's plug screws onto the 9603's SMA connector; its jack takes the Maxtena's SMA-male. Finger-tight only — the antenna's datasheet caps assembly torque at 8 in·lb [D], and a hand on a small SMA nut stays well under it; no tools on SMA. About 100 mm of the cable bends [C], from the drawing's connector lengths.